Universidad de Costa Rica

Reuse Detector: Improving the Management of STT-RAM SLLCs

Ing. Roberto Rodríguez Rodríguez, PhD.
R Rodríguez-Rodríguez and J Díaz and F Castro and P Ibáñez and D Chaver and V Viñals and JC Saez and M Prieto-Matias and L Piñuel and T Monreal and JM Llabería
The Computer Journal


Various constraints of Static Random Access Memory (SRAM) are leading to consider new memory technologies as candidates for building on-chip shared last-level caches (SLLCs). Spin-Transfer Torque RAM (STT-RAM) is currently postulated as the prime contender due to its better energy efficiency, smaller die footprint and higher scalability. However, STT-RAM also exhibits some drawbacks, like slow and energy-hungry write operations that need to be mitigated before it can be used in SLLCs for the next generation of computers. In this work, we address these shortcomings by leveraging a new management mechanism for STT-RAM SLLCs. This approach is based on the previous observation that although the stream of references arriving at the SLLC of a Chip MultiProcessor (CMP) exhibits limited temporal locality, it does exhibit reuse locality, ie …

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