Resumen:
Performance validation and debugging are essential yet time-consuming stages in microprocessor design, often relying on manual analysis of performance counter data. This work explores the use of machine learning to automate the estimation of microprocessor performance, specifically instructions per cycle (IPC), using execution traces collected from the ChampSim simulator. We evaluate multiple feature engineering strategies and ML models, including Random Forest and Gradient Boosted Decision Trees, to identify effective predictors of performance behavior. Our best-performing models achieve over a 45% reduction in prediction error compared to early-stage baselines. These results demonstrate the potential of machine learning to streamline performance validation workflows, reduce manual debugging effort, and enable future automation in microarchitectural analysis.
