Resumen
Due to the lack of information available at early stages of the VLSI design flow, EDA tools are unable to achieve accurate delay estimations in digital circuits, leading to a significant increase of the design convergence time. This work proposes a machine learning-based methodology which, using pre-route delay estimations from an open-source tool, as well as other information available in pre-route stages, improves the accuracy of the delay estimations generated at pre-route stages of OpenLane, an open-source EDA tool. This methodology produces delay estimations that are significantly closer to the signoff delay values, with error reductions of over 67% for circuits that are similar to the ones used to train the models and over 15% in circuits that are completely new to the models, which leads to a faster identification of violations of timing constraints, and an eventual speedup in the design convergence time.
