Resumen:
This study introduces a machine learning-based methodology, that enhances and accelerates the delay estimation of integrated circuits at early design stages, improving the quality of delay estimations at these stages, where EDA tools are usually not very accurate due to the lack of information available. This work seeks to improve delay estimations of OpenLane, and open-source EDA tool, with data available at the placement stage. The proposed methodology leverages the data generated by previous designs, as well as the history of results from previous tool parameter configurations of the design being validated. Our results show that this methodology achieves delay estimations with up to 46% less error than the pre-route estimation of OpenLane, and with runtime reductions up to 80% when the machine learning model has historical data of the design.
