Resumen:
Accurate timing estimation is critical for the design closure of modern digital integrated circuits. However, significant discrepancies often arise between pre-route and signoff delay estimations due to factors such as inaccurate wire load models, and the lack of information regarding the complexities introduced by the routing stage. This paper presents a Machine Learning-based approach that aims to correlate the pre-route and the signoff delay estimations of OpenLane, an open source EDA tool, by predicting the difference (or Delta), between them, with the goal of enhancing early-stage estimation accuracy. Our approach effectively reduces timing uncertainty, enabling faster convergence towards signoff tool quality, and demonstrates potential to streamline the timing closure process. Experimental results show that the proposed model achieves high prediction accuracy, achieving up to 60% RMSE reduction versus the pre-route estimation of the tool by itself. Thus, making it a valuable tool for improving the efficiency of VLSI design methodologies.
