Resumen
Approximate Logic Synthesis (ALS) enables reduced area and power consumption in digital circuits by introducing controlled errors in circuits for error and fault-tolerant applications. Traditional ALS, particularly based on netlist transformation methods, relies on exhaustive simulations to evaluate each approximation's impact, creating a computational bottleneck that limits design space exploration efficiency. This work proposes a machine learning-based approach to predict the error introduced by gate elimination in digital circuits, reducing the need for costly simulations by requiring only a limited number of reference simulations during the iterative design process. We develop a comprehensive feature extraction framework that analyzes up to 154 structural and topological characteristics of circuit netlists, including connectivity patterns, logic levels, controllability, and observability metrics. Our proposed approach, integrated into the AxLS state-of-the-art tool, delivers outstanding speedup for design explorations: up to 700× for a single error evaluation, and up to 28× for a complete design exploration, aimed to find an approximate circuit for a particular error threshold. Our proposed method maintains error estimations within acceptable limits with respect to exhaustive simulations while enabling rapid design space exploration.
